The present invention relates generally to dotting circuits, and more particularly, to a new dotting circuit with an inhibit function for use in electronic engineering change EC circuits and decoder circuits.
There are currently a number of applications which require dotting of two input transistors along with a switching function for switching one of the dotted input transistors into a line while inhibiting the other. One such application is in the context of an electronic engineering change (EC) circuit design for an integrated circuit chip. In order to implement such an electronic EC circuit, a receiver circuit is designed with a first input transistor switch connected to an input/output (I/O) pin whrch is connected to buried wiring in a chip module. This buried wiring could connect, for example, to an I/O of another chip on the module. The EC circuit further includes a second transistor input switch which is connected to an EC pad disposed on the module external to the chip. This EC pad can be used as a land to provide a surface wire connection on the module from this chip to, for example, a different chip to thereby facilitate engineering changes. The signal from only one of these two input transistor switches is to be applied to other circuits in the chip. Some means is thus necessary to switch between the normal input transistor connected to the buried module wiring and the EC transistor switch connected to the external EC pad on the module surface.
Another application requiring circuit dotting in combination with a switching function is a decoder circuit.
A universal logic requirement often imposed on both of these circuit applications is that the resulting circuits simultaneously provide both true and complement outputs. This logic requirement is especially important in collector-switched-emitter-follower (CSEF) circuits, where both true and complementary outputs are normally available. The use of an extra inverter stage in such applications to obtain a complementary output is generally considered to be unacceptable due to the delay which such a stage adds to the circuit speed.
There are a variety of different emitter dotting circuits and collector dotting circuits available in the art for various applications. However, conventional emitter dotting circuits can only provide the complement (out-of-phase) output. Likewise, conventional collector dotting circuits can only provide the true (in-phase) output. Additionally, the dotting of the collectors of two input transistors causes current doubling in the collector resistors when both transistors are biased into conduction. Such current doubling drives the collector voltage of the respective input transistors to a value below their respective base voltages, thereby causing the transistors to saturate. Such saturated transistors have significantly slower switching speeds compared to unsaturated transistor switching speeds. To prevent this transistor saturation, voltage clamps are generally connected across the collector resistors. However, the voltage clamps (typically a diode) act as loads on their collectors and thus slow down the transistor switching speeds.
The invention as claimed is intended to remedy the above-described limitations with conventional dotting circuits. An advantage offered by the present invention is that input transistor switching is obtained in combination with transistor circuit dotting, while simultaneously providing both true and complementary output values from the circuit. A further advantage offered by the present invention is that current in the collector/drain resistors of the input and reference transistors therein is unaffected by the dotting, so that a voltage clamp circuit is unnecessary. Accordingly, the transistor switching delay attendant to the use of voltage clamp circuits is obviated.